This is the project that the DE0 Digital IO Wing is for. I will use the IO wing to level shift the signals from the Gameboy’s LCD screen so my DE0 can capture the data. The Gameboy is a 5V device and the DE0 does not have 5V tolerant IO. I am using a SN74LVC8T245PWR 8-bit directional level shifter to do the translation on the IO wing board.
Purchased a Gameboy DMG-01 off eBay for $20. Needed some cleaning but it worked and had the battery cover!
The Gameboy DMG-01 uses triwing screws. Kidna like philips heads but with 3 “wings” instead of 4. Tool can be found on eBay or Amazon.
The connector between the front and back of the Gameboy is where I will tap into the signals to sneak a peak. Pinout is the following
V-Sync should be 60Hz, Pixel Clock 4Mhz, and H-Sync 9.2kHz.
Connected up the Open Bench Logic Sniffer and powered up the Gameboy with a game in it then ran the capture. I had the trigger set to wait for the V-Sync signal.
Then using my DE0_VGA_Driver I started writing the code take data from RAM on the FPGA and output it on the VGA monitor. I wrote a bitmap to .mif format (memory initialization file) convertor to display some Gameboy screenshots on the VGA Monitor. Link to that repo is here.
Currently working on getting the SN74LVC8T245PWR level shifters working and I will be able to pull live data from the Gameboy LCD data bus.
Design ended up having only 10 LVDS signals broken out as that required less unique parts. The connectors are expensive (1-282834-0) running ~$5.70 in singles. I will be looking into alternatives to see if I can get the cost down. I found some on AliExpress but I will need to order them and test them to see if they are any good.
I also included a 4 position auxiliary power connector to power up external circuits. No power safety though (fuses/TVS) so use at your own risk!
Started work on a expansion board for the DE0 FPGA development board. Planning on having 4 8-bit bi-directional level shifters giving 32 I/O and breaking out 12 LVDS signals to screw terminals. Basically a simple digital acquisition add on. Using the expansion template I made for the DE0 a couple days ago.
LVDS will be buffered to protect the FPGA. Have not picked the buffer chip yet. The bi-directional level shifter is the SN74LVC8T245PWR by Ti. Handles 1.65V to 5.5V on both sides and has basic ESD protection. I am debating putting over voltage protection on the I/O of the level shifters. A 50ohm resistor in series with the I/O plus a 5.6V TVS Diode should do the trick and not add to much cost to the board.
Working on a video driver for the Altera DE0 Development Board by terasIC. The DE0 has a 12bit (4bit per color) resistor ladder DAC that connects to the VGA connector. It is capable of 1280×1024 @ 60Hz officially but I think more is possible.