Boards and parts arrived today from OSH Park and Mouser. Soldered them up after work.
Close up of the board. Not a ton of parts…all connectors. The handle idea worked out pretty well. The board can be pulled out of the dual 40pin headers with ease!
Expansion mounted in the DE0 DEV board. Gotta write up some verilog to test it out now.
Ordered the PCBs from OSH Park. Should be getting them in about two weeks.
Fixed an old bug in some RESET VECTOR DMD display code for multiple lines and got the above demo working. I will have to port the prop code to python however to make my twitter wall thingy.
EDIT// Need to fix some random CSS and the menus but its looking pretty good!
Pulled RESET VECTOR’s 96×16 DMD out of the parts bin and managed to find the old code to get it working again. Going to turn it into a Twitter Feed/Clock/Weather wall thing.
Design ended up having only 10 LVDS signals broken out as that required less unique parts. The connectors are expensive (1-282834-0) running ~$5.70 in singles. I will be looking into alternatives to see if I can get the cost down. I found some on AliExpress but I will need to order them and test them to see if they are any good.
I also included a 4 position auxiliary power connector to power up external circuits. No power safety though (fuses/TVS) so use at your own risk!
Started work on a expansion board for the DE0 FPGA development board. Planning on having 4 8-bit bi-directional level shifters giving 32 I/O and breaking out 12 LVDS signals to screw terminals. Basically a simple digital acquisition add on. Using the expansion template I made for the DE0 a couple days ago.
LVDS will be buffered to protect the FPGA. Have not picked the buffer chip yet. The bi-directional level shifter is the SN74LVC8T245PWR by Ti. Handles 1.65V to 5.5V on both sides and has basic ESD protection. I am debating putting over voltage protection on the I/O of the level shifters. A 50ohm resistor in series with the I/O plus a 5.6V TVS Diode should do the trick and not add to much cost to the board.
GitHub Repository Link!
Uploaded the template that I use for making hardware expansions for the DE0 FPGA Dev board. It fits on the 2 40Pin GPIO Headers on the right side of the board. Files are for Eagle V6.0+
Github repository Link!
Working on a video driver for the Altera DE0 Development Board by terasIC. The DE0 has a 12bit (4bit per color) resistor ladder DAC that connects to the VGA connector. It is capable of 1280×1024 @ 60Hz officially but I think more is possible.
Find the files in the github repository.
Been working on this Keg Cooler the past couple weekends. I picked up a 49″ Milk Cooler on craigslist. It is all stainless construction and has a commercial grade compressor. Very robust.
Five taps on the front. Four for regular CO2 delivery and one nitro tap. Each of the taps have individual control over the serving pressure.
The kegs are accessible from the back. There is enough space for double the amount of kegs but I wanted room for coldcrashing my brews.
This is how the doors open up. I will be adding chain to the lower doors so they cant swing all the way down and damage the taps.