Category Archives: 128×32 LEDDMD

Tweaking the 128×32 LEDDMD Verilog

There was a few problems with the code for the 128×32 LEDDMD. Every so often there was flickering at random spots on the screen. This was because of the way the display memory was updated. I already fixed it by putting a dummy state at the end of the display memory update. Doing so actually increased the speed that data could be sent to the FPGA. There is no waiting between the Latch pulls.

The last problem is that there is some slight ghosting on the screen. Due to the way the screen updates it looks like the Column data is updating slightly before the rows are updated. Because of this you get a ghost effect on the opposite side of the screen that is up one row.

I think the reason why is because there is a slight delay in the rows caused by the decoders. The current plan of attack is to buffer the Column data a couple cycles before outputting.

LEDDMD 128×32 Complete

So I finally finished the prototype of the 128 x 32 Light Emitting Diode Dot Matrix Display V1.0 (LEDDMD). The protocol to write to the display is almost exactly like a shift register. There is a clock, latch, and data lines. It works in either 1 bit mode or 8 bit mode data line modes.

In 1 bit mode there is only 1 data line and in 8 bit mode this is 8 data lines. 8 bit mode enables you to clock in an entire byte of data at a time speeding up the transfer process by a factor of 8. In either mode you can do animations smoothly. All processing of the data is done on the microcontroller. The Display stores the data and takes care of running the display.

The bulk of the hardware is in the FPGA. I am using a Cyclone II EP2C8Q208C8N FPGA breakout board. There are some darlington transistor arrays that sink the current from a single row. To expand the I/O of the FPGA some decoders are used.

Here are the links to all the code:
Main Routine

Transmission Protocol and Test

128×32 DMD Update

The verilog code is almost fully debugged. The demo code that will run on a Parallax Propeller is in the works. Right now the demo is fairly basic. Today I wrote a C program that takes a 4-bit bitmap image and strips out the header and and converts it to a 2-bit image. It then reorientates the data so the image is “correct”. Bitmap images data reads the image from bottom left to top right. This is essentially backwards. So the program corrects this which means less work for the microcontroller and faster transmission of pixels.

32×128 DMD Rat Lining Halfway Done

Halfway done with the rat lining for the PCB. A rat line is basically a visible line while PCB drawing that indicates net lists. A net list is just a list of all the pins and connections that are connected together. After I rat line I can lay down the traces.

The FPGA sees the display as a 64×64. This is due to I/O limitations. The odd rows are on the left and the even rows are on the right. So row 1 and 2 really make up the physical row 1.