module matrix
(
	clk,row,col,SDRAM_CS,SRAM_CS
);

input	wire		clk;

output	reg [0:15]	row;
output	reg [0:15]	col;
output  reg [0:0] 	SDRAM_CS;
output  reg [0:0] 	SRAM_CS;
		reg [24:0]  clk_slow;
		reg [4:0]	row_cnt;

initial 
	begin
	row <= 16'b1000000000000000;
	col <= 16'b0000000000000000;
	SDRAM_CS <= 1'b0;
	SRAM_CS <= 1'b0;
	clk_slow <= 16'b0000000000000000;
	row_cnt <= 4'b0000;
	end
	
always @(posedge clk) clk_slow=clk_slow + 1'b1;	

always @(posedge clk_slow[14]) 
	begin
	
	row <= {row[15],row[0:14]};
		if(row_cnt[0])
			begin
			col <= 16'b0101010101010101;
			end
		else
			begin
			col <= 16'b1010101010101010;
			end
	row_cnt <= row_cnt + 1'b1;
	
	//col <= 16'b1111111111111111;
	
	end
endmodule