module matrix
(
	clk,row,col,SDRAM_CS,SRAM_CS,LAT,DATA,SCLK
);

input	wire		clk;
input	wire		LAT;
input	wire		DATA;
input	wire		SCLK;

output	reg [0:15]	row;
output	reg [15:0]	col;
output  reg [0:0] 	SDRAM_CS;
output  reg [0:0] 	SRAM_CS;

		reg [24:0]  clk_slow;
		reg [4:0]	row_cnt;
		reg [255:0]	col_buffer;
		reg [15:0]	col_temp [15:0];

initial 
	begin
		row <= 16'b0000000000000001;
		col <= 16'b0000000000000000;
		SDRAM_CS <= 1'b0;
		SRAM_CS <= 1'b0;
		clk_slow <= 16'b0000000000000000;
		row_cnt <= 5'b00000;
	end
	
always @(posedge clk) clk_slow=clk_slow + 1'b1;	

always @(posedge clk_slow[10]) 
begin
	if(row_cnt > 5'b01111)
	begin
		row_cnt <= 5'b00000;
	end
	col <= col_temp[row_cnt];	
	row_cnt <= row_cnt + 1'b1;
	row <= {row[15],row[0:14]};
	
end
	
always @(posedge SCLK)
begin
	if(LAT)
	begin
		col_buffer <= {col_buffer[254:0],DATA};
	end
	else
	begin
		col_temp [0] <= col_buffer [255:240];
		col_temp [1] <= col_buffer [239:224];
		col_temp [2] <= col_buffer [223:208];
		col_temp [3] <= col_buffer [207:192];
		col_temp [4] <= col_buffer [191:176];
		col_temp [5] <= col_buffer [175:160];
		col_temp [6] <= col_buffer [159:144];
		col_temp [7] <= col_buffer [143:128];
		col_temp [8] <= col_buffer [127:112];
		col_temp [9] <= col_buffer [111:96];
		col_temp [10] <= col_buffer [95:80];
		col_temp [11] <= col_buffer [79:64];
		col_temp [12] <= col_buffer [63:48];
		col_temp [13] <= col_buffer [47:32];
		col_temp [14] <= col_buffer [31:16];
		col_temp [15] <= col_buffer [15:0];
	end
end
endmodule