module LED_Matrix_32x128
(
	clk,e_cnt,row_cnt,col,SDRAM_CS,SRAM_CS,LAT,INPUT,SCLK,EN
);

input	wire	clk;
input	wire	LAT;
	reg	LAT_1;
	reg	LAT_2;
	reg SCLK_1;
	reg SCLK_2;
input	wire	[7:0]	INPUT;
input	wire	SCLK;
input	wire	EN;

output	reg [63:0]	col;
output  reg [0:0] 	SDRAM_CS;
output  reg [0:0] 	SRAM_CS;
output  reg [3:0]	row_cnt;
output	reg [3:0]	e_cnt;

		reg [24:0]  clk_slow;
		reg [4095:0]	col_buffer /* synthesis noprune */;
		reg [1:0]	count; 
		
		reg	[5:0]	read_addr;
		reg	[5:0]	write_addr;
		reg	[127:0]	disp_mem_data;
		reg			disp_mem_wren;
		wire	[127:0]	disp_mem_q;
		reg [0:0]	eol;
		
		reg	[5:0]	sel;
		reg [0:0]	update;
		
		reg	[5:0]	read_addrn;
		reg	[5:0]	write_addrn;
		reg	[127:0]	disp_mem_datan;
		reg			disp_mem_wrenn;
		wire	[127:0]	disp_mem_qn;
		
initial 
	begin
		SDRAM_CS <= 1'b0;
		SRAM_CS <= 1'b0;
		clk_slow <= 16'b0000000000000000;
		row_cnt <= 4'b1111; //144
		e_cnt <= 4'b0111;
		write_addr <= 6'b000000;
		read_addr <= 6'b000000; 
		read_addrn <= 6'b000000;
		disp_mem_wren <= 0;
		write_addrn <= 6'b000000;
		disp_mem_wrenn <= 0;
		sel <= 6'b000000;
		count <= 2'b00;
	end


always @(posedge clk)
begin
	LAT_2 <= LAT_1;
	LAT_1 <= LAT;
	
	SCLK_2 <= SCLK_1;
	SCLK_1 <= SCLK;
end

always @(posedge clk) 
begin
	clk_slow <= clk_slow + 1'b1;
	
	if((!LAT_2)) //&& (eol == 1'b1))
	begin
	case(sel)
		6'b000000:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[4095:3968];
			sel <= 6'b000001;
		end
		6'b000001:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[3967:3840];
			sel <= 6'b000010;
		end
		6'b000010:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[3839:3712];
			sel <= 6'b000011;
		end
		6'b000011:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[3711:3584];
			sel <= 6'b000100;
		end
		6'b000100:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[3583:3456];
			sel <= 6'b000101;
		end
		6'b000101:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[3455:3328];
			sel <= 6'b000110;
		end
		6'b000110:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[3327:3200];
			sel <= 6'b000111;
		end
		6'b000111:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[3199:3072];
			sel <= 6'b001000;
		end
		6'b001000:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[3071:2944];
			sel <= 6'b001001;
		end
		6'b001001:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[2943:2816];
			sel <= 6'b001010;
		end
		6'b001010:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[2815:2688];
			sel <= 6'b001011;
		end
		6'b001011:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[2687:2560];
			sel <= 6'b001100;
		end
		6'b001100:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[2559:2432];
			sel <= 6'b001101;
		end
		6'b001101:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[2431:2304];
			sel <= 6'b001110;
		end
		6'b001110:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[2303:2176];
			sel <= 6'b001111;
		end
		6'b001111:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[2175:2048];
			sel <= 6'b010000;
		end
		6'b010000:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[2047:1920];
			sel <= 6'b010001;
		end
		6'b010001:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[1919:1792];
			sel <= 6'b010010;
		end
		6'b010010:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[1791:1664];
			sel <= 6'b010011;
		end
		6'b010011:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[1663:1536];
			sel <= 6'b010100;
		end
		6'b010100:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[1535:1408];
			sel <= 6'b010101;
		end
		6'b010101:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[1407:1280];
			sel <= 6'b010110;
		end
		6'b010110:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[1279:1152];
			sel <= 6'b010111;
		end
		6'b010111:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[1151:1024];
			sel <= 6'b011000;
		end
		6'b011000:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[1023:896];
			sel <= 6'b011001;
		end
		6'b011001:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[895:768];
			sel <= 6'b011010;
		end
		6'b011010:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[767:640];
			sel <= 6'b011011;
		end
		6'b011011:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[639:512];
			sel <= 6'b011100;
		end
		6'b011100:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[511:384];
			sel <= 6'b011101;
		end
		6'b011101:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[383:256];
			sel <= 6'b011110;
		end
		6'b011110:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[255:128];
			sel <= 6'b011111;
		end
		6'b011111:
		begin
			if (!EN) write_addrn <= sel;			
			else write_addrn <= 6'b100000 | sel;
			disp_mem_wrenn <= 1'b1;
			disp_mem_datan <= col_buffer[127:0];
			sel <= 6'b100000;
		end
		6'b100000:
		begin
			disp_mem_wrenn <= 1'b0;
			sel <= 6'b100000;
			if(EN)
			begin	
				write_addr <= 6'b000000; 
				read_addrn <= 6'b000000;
				disp_mem_wren <= 1'b1;
				sel <= 6'b100001;
			end
		end
		6'b100001:
		begin
			disp_mem_data <= disp_mem_qn;
			sel <= 6'b100010;
		end
		6'b100010:
		begin
			read_addrn <= read_addrn + 1'b1;
			write_addr <= write_addr + 1'b1;
			sel <= 6'b100011;
		end
		6'b100011:
		begin
			sel <= 6'b100100;
		end
		6'b100100:
		begin
			sel <= 6'b100101;
		end
		6'b100101:
		begin
			sel <= 6'b100001;
		end
		default: 
		begin
			sel <= 6'b000000;
			write_addrn <= 6'b000000;
			disp_mem_wrenn <= 1'b0;
			disp_mem_wren <= 1'b0;
		end
	endcase
	end
	else if(LAT_2)
	begin
		disp_mem_wrenn <= 1'b0;
		disp_mem_wren <= 1'b0;
		write_addrn <= 6'b000000;
		write_addr <= 6'b000000; 
		read_addrn <= 6'b000000;
		sel <= 6'b000000;
	end
end

always @(posedge clk_slow[10]) 
begin
	if(row_cnt == 4'b1111)
	begin
		//row_cnt <= 5'b00000;
		e_cnt <= {e_cnt[2:0],e_cnt[3]};
		col <= 64'b0000000000000000000000000000000000000000000000000000000000000000;
		//eol <= 1'b1;
	end
	//eol <= 1'b0;

	if (disp_mem_q[127:126] > count) col[0] <= 1'b1;
	else col[0] <= 1'b0;
	if (disp_mem_q[125:124] > count) col[1] <= 1'b1;
	else col[1] <= 1'b0;
	if (disp_mem_q[123:122] > count) col[2] <= 1'b1;
	else col[2] <= 1'b0;
	if (disp_mem_q[121:120] > count) col[3] <= 1'b1;
	else col[3] <= 1'b0;
	if (disp_mem_q[119:118] > count) col[4] <= 1'b1;
	else col[4] <= 1'b0;
	if (disp_mem_q[117:116] > count) col[5] <= 1'b1;
	else col[5] <= 1'b0;
	if (disp_mem_q[115:114] > count) col[6] <= 1'b1;
	else col[6] <= 1'b0;
	if (disp_mem_q[113:112] > count) col[7] <= 1'b1;
	else col[7] <= 1'b0;
	if (disp_mem_q[111:110] > count) col[8] <= 1'b1;
	else col[8] <= 1'b0;
	if (disp_mem_q[109:108] > count) col[9] <= 1'b1;
	else col[9] <= 1'b0;
	if (disp_mem_q[107:106] > count) col[10] <= 1'b1;
	else col[10] <= 1'b0;
	if (disp_mem_q[105:104] > count) col[11] <= 1'b1;
	else col[11] <= 1'b0;
	if (disp_mem_q[103:102] > count) col[12] <= 1'b1;
	else col[12] <= 1'b0;
	if (disp_mem_q[101:100] > count) col[13] <= 1'b1;
	else col[13] <= 1'b0;
	if (disp_mem_q[99:98] > count) col[14] <= 1'b1;
	else col[14] <= 1'b0;
	if (disp_mem_q[97:96] > count) col[15] <= 1'b1;
	else col[15] <= 1'b0;
	if (disp_mem_q[95:94] > count) col[16] <= 1'b1;
	else col[16] <= 1'b0;
	if (disp_mem_q[93:92] > count) col[17] <= 1'b1;
	else col[17] <= 1'b0;
	if (disp_mem_q[91:90] > count) col[18] <= 1'b1;
	else col[18] <= 1'b0;
	if (disp_mem_q[89:88] > count) col[19] <= 1'b1;
	else col[19] <= 1'b0;
	if (disp_mem_q[87:86] > count) col[20] <= 1'b1;
	else col[20] <= 1'b0;
	if (disp_mem_q[85:84] > count) col[21] <= 1'b1;
	else col[21] <= 1'b0;
	if (disp_mem_q[83:82] > count) col[22] <= 1'b1;
	else col[22] <= 1'b0;
	if (disp_mem_q[81:80] > count) col[23] <= 1'b1;
	else col[23] <= 1'b0;
	if (disp_mem_q[79:78] > count) col[24] <= 1'b1;
	else col[24] <= 1'b0;
	if (disp_mem_q[77:76] > count) col[25] <= 1'b1;
	else col[25] <= 1'b0;
	if (disp_mem_q[75:74] > count) col[26] <= 1'b1;
	else col[26] <= 1'b0;
	if (disp_mem_q[73:72] > count) col[27] <= 1'b1;
	else col[27] <= 1'b0;
	if (disp_mem_q[71:70] > count) col[28] <= 1'b1;
	else col[28] <= 1'b0;
	if (disp_mem_q[69:68] > count) col[29] <= 1'b1;
	else col[29] <= 1'b0;
	if (disp_mem_q[67:66] > count) col[30] <= 1'b1;
	else col[30] <= 1'b0;
	if (disp_mem_q[65:64] > count) col[31] <= 1'b1;
	else col[31] <= 1'b0;
	if (disp_mem_q[63:62] > count) col[32] <= 1'b1;
	else col[32] <= 1'b0;
	if (disp_mem_q[61:60] > count) col[33] <= 1'b1;
	else col[33] <= 1'b0;
	if (disp_mem_q[59:58] > count) col[34] <= 1'b1;
	else col[34] <= 1'b0;
	if (disp_mem_q[57:56] > count) col[35] <= 1'b1;
	else col[35] <= 1'b0;
	if (disp_mem_q[55:54] > count) col[36] <= 1'b1;
	else col[36] <= 1'b0;
	if (disp_mem_q[53:52] > count) col[37] <= 1'b1;
	else col[37] <= 1'b0;
	if (disp_mem_q[51:50] > count) col[38] <= 1'b1;
	else col[38] <= 1'b0;
	if (disp_mem_q[49:48] > count) col[39] <= 1'b1;
	else col[39] <= 1'b0;
	if (disp_mem_q[47:46] > count) col[40] <= 1'b1;
	else col[40] <= 1'b0;
	if (disp_mem_q[45:44] > count) col[41] <= 1'b1;
	else col[41] <= 1'b0;
	if (disp_mem_q[43:42] > count) col[42] <= 1'b1;
	else col[42] <= 1'b0;
	if (disp_mem_q[41:40] > count) col[43] <= 1'b1;
	else col[43] <= 1'b0;
	if (disp_mem_q[39:38] > count) col[44] <= 1'b1;
	else col[44] <= 1'b0;
	if (disp_mem_q[37:36] > count) col[45] <= 1'b1;
	else col[45] <= 1'b0;
	if (disp_mem_q[35:34] > count) col[46] <= 1'b1;
	else col[46] <= 1'b0;
	if (disp_mem_q[33:32] > count) col[47] <= 1'b1;
	else col[47] <= 1'b0;
	if (disp_mem_q[31:30] > count) col[48] <= 1'b1;
	else col[48] <= 1'b0;
	if (disp_mem_q[29:28] > count) col[49] <= 1'b1;
	else col[49] <= 1'b0;
	if (disp_mem_q[27:26] > count) col[50] <= 1'b1;
	else col[50] <= 1'b0;
	if (disp_mem_q[25:24] > count) col[51] <= 1'b1;
	else col[51] <= 1'b0;
	if (disp_mem_q[23:22] > count) col[52] <= 1'b1;
	else col[52] <= 1'b0;
	if (disp_mem_q[21:20] > count) col[53] <= 1'b1;
	else col[53] <= 1'b0;
	if (disp_mem_q[19:18] > count) col[54] <= 1'b1;
	else col[54] <= 1'b0;
	if (disp_mem_q[17:16] > count) col[55] <= 1'b1;
	else col[55] <= 1'b0;
	if (disp_mem_q[15:14] > count) col[56] <= 1'b1;
	else col[56] <= 1'b0;
	if (disp_mem_q[13:12] > count) col[57] <= 1'b1;
	else col[57] <= 1'b0;
	if (disp_mem_q[11:10] > count) col[58] <= 1'b1;
	else col[58] <= 1'b0;
	if (disp_mem_q[9:8] > count) col[59] <= 1'b1;
	else col[59] <= 1'b0;
	if (disp_mem_q[7:6] > count) col[60] <= 1'b1;
	else col[60] <= 1'b0;
	if (disp_mem_q[5:4] > count) col[61] <= 1'b1;
	else col[61] <= 1'b0;
	if (disp_mem_q[3:2] > count) col[62] <= 1'b1;
	else col[62] <= 1'b0;
	if (disp_mem_q[1:0] > count) col[63] <= 1'b1;
	else col[63] <= 1'b0;
	
	if (read_addr == 6'b111111) count <= count + 1'b1;
	read_addr <= read_addr + 1'b1;	
	row_cnt <= row_cnt + 1'b1;
	//end
end
	
always @(posedge SCLK_2)
begin
	if(LAT_2)
	begin		
		col_buffer <= {col_buffer[4087:0],INPUT[7:0]};//{col_buffer[4093:0],2'b01};
	end
	
	//else if(sel == 6'b100000)
	//begin
	//	col_buffer <= 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
	//end
end

display_memory disp_mem_inst (
        .rdaddress (read_addr),
        .wraddress (write_addr),
        .clock  (clk),
        .data   (disp_mem_data),
        .wren   (disp_mem_wren),
        .q      (disp_mem_q)
);

display_memory disp_mem_instn (
        .rdaddress (read_addrn),
        .wraddress (write_addrn),
        .clock  (clk),
        .data   (disp_mem_datan),
        .wren   (disp_mem_wrenn),
        .q      (disp_mem_qn)
);

endmodule