DE0 Digital I/O Wing Expansion

Schematic

Started work on a expansion board for the DE0 FPGA development board. Planning on having 4 8-bit bi-directional level shifters giving 32 I/O and breaking out 12 LVDS signals to screw terminals. Basically a simple digital acquisition add on. Using the expansion template I made for the DE0 a couple days ago.

LVDS will be buffered to protect the FPGA. Have not picked the buffer chip yet. The bi-directional level shifter is the SN74LVC8T245PWR by Ti. Handles 1.65V to 5.5V on both sides and has basic ESD protection. I am debating putting over voltage protection on the I/O of the level shifters. A 50ohm resistor in series with the I/O plus a 5.6V TVS Diode should do the trick and not add to much cost to the board.

Layout

GitHub Repository Link!

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